The present invention relates generally to methods and structures for forming semiconductor devices with reduced contact resistance.
An integrated circuit (IC) generally includes a semiconductor substrate in which a number of device regions are formed by diffusion or ion implantation of suitable dopants. This substrate usually includes a passivating layer and an insulating layer, which are required in order to form different device regions. The total thickness of these layers is usually less than one micron. Openings through these layers (called vias or contact holes) and trenches therein allow electrical contact to be made selectively to the underlying device regions. A conducting material such as copper is used to fill these holes, which then make contact to semiconductor devices